Peripheral Component Interconnect express (PCIe) (as described, for example, in The PCI Express Base Specification of the PCI Special Interest Group, Revision 3.0 published Nov. 18, 2010) describes an interconnection standard for coupling peripheral devices to a host computing system. The host computing system will include a root complex, multiple endpoints (i.e., peripheral devices) and a switch.
The root complex denotes the root of an input/output (I/O) hierarchy that connects the host microprocessor and memory subsystem to the I/O. The root complex will support one or more PCIe ports connected to a single endpoint. The switch will control which point-to-point serial connections between each endpoint and the host system are active, while the root complex manages these connections. Currently, there exists no solution to have a plurality of point-to-point serial connections for a plurality of endpoints managed as a single connection by the root complex. This prevents solutions that merge devices (e.g., cache-use models, Redundant Array of Independent Disk (RAID) memory system models) from utilizing PCIe connections.
Descriptions of certain details and implementations follow, including a description of the figures, which may depict some or all of the embodiments described below, as well as discussing other potential embodiments or implementations of the inventive concepts presented herein. An overview of embodiments of the invention is provided below, followed by a more detailed description with reference to the drawings.